A typical integrated circuit contains a plurality of metal pathways to provide electrical power for powering the various semiconductor devices comprising the integrated circuit, and to allow these semiconductor devices to share/exchange electrical information. Within integrated circuits, metal layers are stacked on top of one another by using intermetal or "interlayer" dielectrics that insulate the metal layers from each other. Typically, however, each metal layer must form electrical contact to an additional metal layer.
Metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers to be connected, and by filling the resulting hole or via with a metal (creating an "interconnect"). In a conventional dual damascene process, a "line" or trench is first etched in the interlayer dielectric followed by the formation of a via therein (i.e., a line first dual damascene process). Both the line and the via then are filled with a metal to create an interconnect.
Because variations in line density across a semiconductor chip produce thickness variations in the photoresist ("resist") used to image vias during a line first dual damascene process, the reproducible production of small vias across a semiconductor chip is difficult using conventional line first dual damascene processes. One method for overcoming this problem is to partially or completely etch each via prior to line formation, and to thereafter re-mask, define and etch each line (i.e., a via first dual damascene process). However, removing line imaging resist (and/or anti-reflective coating) from vias is difficult, especially for high aspect ratio vias (e.g., vias having aspect ratios that exceed three). Any residual line imaging resist remaining within a via blocks contact to the underlying metal layer and degrades/inhibits interconnect formation. Accordingly, a need exists for methods for forming improved metal interconnects.